Sessions Details
Use of computer simulation to optimise thermal design of military electronics systems.
Increasingly designers are being pushed towards producing smaller pieces of equipment containing more powerful electronics. As a result this equipment is producing more heat which is more difficult to dissipate. Given the harsh environments that military hardware has to operate in and calls for high reliability this is a growing issue. Designers are unable to rely on cooling devices which can be used in less critical applications so have to turn to more innovative methods.
The problem is that these ideas have to be tested. Traditionally this may take the form of a prototype test to prove that a technique works. However, more often than not the design is not ideal and requires modification and lengthy re-testing at high cost in both time and money. A solution is the use of computer simulation during all design stages to investigate design concepts and to test the final design prior to prototype testing.
This paper discusses the computer simulation technique known as Computational Fluid Dynamics (cfd) as applied to the field of electronics design. The paper introduces the technology and illustrates how it can be used in this application area. Further, validation studies are discussed to demonstrate the accuracy of such techniques.
Even if a design works it may not be the optimum in terms of performance and cost. This paper discusses the extension of cfd techniques to automatically optimise the design avoiding the need for over engineering to achieve acceptable cooling.
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Case Study: COTS VME Processing Comparison of 4-Way SMP Intel Vs. Quad Distributed PowerPC.
Many military deployed environments depend on the VME infrastructure to provide the ruggedness, reliability, and performance to meet the mission requirements. The development cycle of a military application typically begins on commodity workstations or servers. Implementation is then moved to VME-based processors, often requiring a non-trivial porting effort. If the processing demands are small, a VME solution of similar architecture often can be found, mitigating the porting effort. More challenging applications, such as those demanding several processors working in unison, may require a complete architecture change when transitioning from development platforms to deployment hardware.
With the recent availability of Dual-Core Intel® Xeon® processors, it will soon be possible to deploy VME systems with workstation processors in familiar Symmetric Multi-Processing (SMP) configurations, pushing the development cycle onto deployment hardware. This presentation compares that new architecture to two existing distributed-multiprocessing architectures. The first comparison is against distributed Intel mobile processors applied to general-purpose processing and I/O, such as in a mission computer. The second comparison is against distributed PowerPC processors with AltiVec technology applied to digital signal processing, such as found in a radar processor or other ISTAR application. Both comparisons include benchmarks on performance for size, weight, and power.
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Design and verification issues with SERDES technologies for military and aerospace applications.
Military and Aerospace applications have always demanded high bandwidth between processing elements
in the electronic subsystems to enable to the performance of the complex signal processing tasks
required by such applications as Threat Detection, Target Acquisition and ECM (Electronic Counter Measures).
In the past these high bandwidth interfaces have often been based on bespoke protocols and technologies.
However, the increasing demand for military and aerospace applications to use commercial off the shelf
(COTS) technologies for cost reduction has led to the utilisation of the current generation of SERDES
(SERializer/DESerializer) technologies primarily developed for the computer and telecommunications industries
to be adopted. This paper will examine the design and verification issues that occur when these new
SERDES technologies are adopted and propose some changes to the electronic design methodology
to address these challenges.
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Exemption Overruled: - Practicalities of COTS, design force defence contractors to confront lead-free.
Despite the best intentions of legislators, Europe’s defence industry must respond to challenges imposed by the economic realities of the global drive toward lead-free electronics.
Military equipment is one of the product categories exempted in the EU RoHS and WEEE directives coming into force from July 2006. However, in reality the widespread use of COTS components in military equipment is forcing defence contractors into the lead-free front line. This is because commercial component manufacturers cannot economically convert their entire catalogue to lead-free, and are instead withdrawing some components from the market. Most of these are now superseded for commercial applications, but the long-term support requirements for military products can spell problems for defence contractors. All components, from passives to semiconductors to LCDs, are affected.
Europe’s defence contractors, therefore, may be forced to divert their highly paid design teams into time-consuming sustaining engineering tasks. This will naturally divert resource away from R&D, putting those businesses at risk of falling behind competitors operating in other territories.
This paper goes on to discuss:
- The temptation of last time buying of stocks
- Outsourcing the re-designs with care
- Establishing control from the beginning - Partners and Project Management
- Responding to change and getting help!
COTS and Reliability
The use of commercial or COTS components in the aerospace industry is increasing exponentially. End users are expecting higher levels of reliability and maintainability and are concerned that COTS components may not meet these requirements.
The immediate concerns are what is a component user buying when a COTS component is procured and how reliable will individual components be.
IGG has been evaluating new COTS components intended for space applications and analysing field failures from the wider military and avionics field since 1998
The presentation will consider:
- Identifying counterfeit components
- Recent experiences in the failure analysis of COTS components
- The failure mechanisms which are predominant today
- The results of reliability testing
- IGG's latest results in the study of components with pure tin (Sn) lead finish including copper tin intermetallics on pure tin lead finishes.
- Long term storage of COTS.
Leveraging the individual strengths of DSPs and FPGAs into a single hybrid architecture.
Despite amazing advances in technology, high-performance and hard real-time signal processing has always been and will probably always be a serious challenge. These are the applications that require multiple processing elements, often on multiple boards, with relentlessly high data rates. Exacerbating the problem is the fact that as the technology improves, the expectations of the users and the definition of what is high-performance keeps changing.
Until recently, the same basic approach was to put either as many FPGAs or DSPs on a given board format as possible. But whether it is more DSPs or more FPGAs, each of these approaches is simple brute force, and with each board generation, the design becomes more complex, more expensive, and much more power hungry. Despite this, application requirements are still outpacing technology improvements. The old paradigms aren’t working and a different approach must be developed that leverages the individual strengths of DSPs and FPGAs into a single hybrid architecture in which the whole is greater than the sum of the parts.
The need to use the “correct” compute elements when solving a problem will be discussed in this paper, along with the necessity for an I/O and compute framework that enables the moving of data between the “correct” compute elements for different parts of the application. This would include a framework to manage the processing and routing of data. Ease-of-use when going through the design process is also becoming a necessary piece of the puzzle, creating a requirement for standard I/O interfaces, messaging SW, packets, libraries, and an RTOS. Lastly, common design issues including control plane/data plane, power consumption, and thermal management will be discussed.
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Design of net-centric warfare systems using open standards middleware to ensure interoperability and ease of integration.
A key aspect of the design of Net-Centric warfare systems involves the integration of systems and components developed by multiple suppliers. Furthermore, this process needs to continue over long project life cycles as legacy systems are continuously maintained, updated and renewed. The Net itself continuously grows and will need to accommodate requirements that, despite best efforts, will fail to be predicted exactly. The challenge is to develop applications that can and will evolve in capability and functionality as the net-centric warfare system itself develops in scope and size.
The NATO C3 Technical Architecture calls for:
- Interoperability within NATO Systems
- Effective implementation of NATO CIS
- Nation to Nation Systems Interoperability
While individual nations and suppliers may differentiate their solutions based on their methods of development, selection of packaging, execution, storage and network transport
technologies, the one thing that can be agreed upon relatively easily is the data that needs to be shared within the Net-Centric warfare system. By leveraging a common definition of the data and using it to specify the application, the system becomes far more interoperable and readily integrated. And by basing the distribution of that data on open standards & COTS based technologies such as DDS and SQL, the systems also become cheaper to design, integrate and maintain, as well as providing more predictable development schedules.
This paper will present and demonstrate the use of a data-oriented standards-based design methodology in Net-Centric warfare applications. Examples will be give of the adoption and deployment of COTS/open standards technologies such as DDS (Data Distribution Service) in multiple US DoD programs such as Navy OA (Open Architecture), SOSCOE and FCS.
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Software Defined Radio: – Enabling technology for network centric capability.
A Software Defined Radio (SDR) is a wireless system whose functions can be defined and reconfigured independent of the target hardware. SDR offers significant performance and economic advantages. A single platform can perform multiple functions while at the same time reducing the amount of equipment required in the field, decreasing life cycle maintenance costs and allowing for re-use and portability of application software. SDR is primarily recognized as an enabling technology for interoperable communications and associated with new generation military radio programs such as the US DoD’s Joint Tactical Radio System (JTRS). However, SDR is being applied to several other applications within the digital battlefield, including deployable ad-hoc networks, reconfigurable MilSatCom terminals and multi-mission UAV payloads.
This presentation will:
- Provide a technical overview of Software Defined Radio (SDR)
- Describe the Software Communications Architecture (SCA) developed by the US DoD and adopted by the international SDR Forum. The SCA is the key component of SDR platforms being deployed in military programmes today.
- Give several examples of SDR programmes underway today in North America and throughout Europe.
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UML traceability in safety-critical systems.
The Unified Modelling Language (UML) has become the de facto standard notation for software systems. The safety-critical development community has resisted adoption of UML since it is perceived to be unable to provide a fully traceable solution. It can be argued that traceability is the inverse of process; therefore a strong process will yield a traceable design. The Pragma process is introduced for defining consistent, traceable models using UML 2.0. At each stage the trace evidence will be highlighted.
The following topics will be discussed:
- The importance of scenario-driven design
The concept of traceability through message equivalence – Using sequence diagrams to maintain traceability Generating state diagrams from sequence diagrams The capture of design justification - Requirements analysis:
Requirements models in UML Why the Use Case diagram alone is inadequate for fully specifying software requirements. The trinity of requirements models: use case, modes and context. - The ‘Ideal’ object model
The benefits of developing a computationally-independent model Using the Software Architecture Document to capture design justification - The Specification model
Defining active and passive objects Defining state behaviour for active objects Using state space analysis to verify state models - The Tasking model
The orthogonal nature of the object model and the tasking model Translating active objects to tasks. The importance and function of an Implementation document - From models to code.
Getting from state behaviour to module specifications. Creating a class hierarchy to give code taxonomy Using the activity diagram to specify algorithmic behaviour
Security and Safety without Compromise
Core to the future of developing a successful secure, reliable and safe system is the ability to develop using the Multiple Independent Levels of Security (MILS) architecture or a partition-based ARINC 653-1 architecture.
This presentation will describe a solution to the vision of streamlining secure network computing in a number of environments (e.g. government, military) that require multiple levels of security from unclassified to top secret running on a single computer using multiple secure partitions. This reduces the number of physical machines on the desktop and allows data to move from one partitioned system to another (e.g. unclassified to secret) on a single physical machine.
The presentation will also refer to DO-178B Level A artefact augmentation and reuse to satisfy MILS requirements, and to evaluation using the most stringent SKPP (Separation Kernel Protection Profile) of Common Criteria EAL6+.
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Reusability of software for safety-critical systems.
A quantum leap has been achieved with reusability of software for safety-critical systems. Previously, any software used in airborne systems could only be approved when installed on a hardware platform in an aircraft environment. A new policy released by the Federal Aviation Administration in December 2004, called Advisory Circular 20-148, recognizes that software components can be accepted as meeting RTCA/DO-178B guidelines independent of a hardware platform. The Reusable Software Component (RSC) process allows for “portability” of the certification effort across hardware platforms and projects enabling economies not previously seen in safety critical software development. The RSC is an important aspect of controlling software development costs as well as improving time-to-market and quality of software systems, especially where the system needs to go through a rigorous certification process. This paper examines the benefits of following AC 20-148 guidance as well as how RSC acceptance of a time-space partitioned Real Time Operating System has been achieved. << Back to conference programme
Combining the software flexibility of an Open Core and hardware flexibility of FPGAs.
When faced with the task of selecting a programmable HW platform for a
system, a designer has the choice of using a catalogue product or an ASSP
or having a chip designed on purpose for his system.
The former devices generally offer a good ecosystem. They are supported by
a wide range of software algorithms and operating systems and the user has
a broad range of tools to choose from. On the low side, they are rarely a
perfect fit in terms of peripheral combination. In most cases, the hardware
designer will need some companion chip to complement his microprocessor
and provide the required interfaces for sensors, actuators and busses.
An ASIC on the other hand can be specified to offer the exactly required
interfaces. This can also be combined with the benefits of an open core in the
same way as an ASSP or catalogue product, but generally a high volume is
needed to justify the cost of an ASIC development. A further drawback is
obviously its limited reusability.
This flexibility of reuse is offered by FPGAs. These devices can be
reprogrammed and configured to be a perfect fit for a given system. But using
a powerful CPU supported by an adequate ecosystem has so far been
difficult. This is why FPGAs have often been used in combination with a
catalogue microprocessor to provide the missing peripheral blocks.
In this presentation, we suggest to show how to combine the best of both
worlds. By using an ARM core in combination with an FPGA, the designer
gets access to the ecosystem of the industry standard CPU for optimal
software development support whilst keeping the hardware flexibility of
FPGAs.
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Requirements for a COTS MILS operating system.
As Force Transformation drives increasingly interconnected systems, daunting security challenges loom. Computers no longer work in isolation. Classified data is no longer protected in silos. The entire system must be networked, presenting a single view of the battle space, when and where the warfighter needs it.
As this vision becomes reality, the responsibility for information security is shifting from the user to the software.
At the foundation of software security is the operating system. For the embedded world, this foundation is the Real-Time Operating System (RTOS). Learn how security-critical (MILS) and safety-critical OS designs, based on the Common Criteria (ISO/IEC 15408) security and the RTCA/DO-178B flight safety standards, are leveraging ARINC 653 time and space partitioning to bring information security to complex, multi-tasking, networked systems.
The software industry cannot deliver on this promise alone. It is only through the convergence of COTS technology, industry standards, certification authorities, and close government-industry cooperation, that this vital national interest will become a reality.
Objectives:
- Discuss the critical importance of COTS and standards to the ultimate success of connected warfare (Network Centric Operations)
- Discuss security as a pre-requisite for networked systems.
- Discuss the commonalities among MILS and ARINC 653 solutions, and DO-178B and Common Criteria certifications.
- Discuss the Common Criteria certification process.
- Summarize industry progress towards a MILS solution, and vision for the future.
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Avionics Full Duplex Switched Ethernet (AFDX).
This Technical paper provides an overview of the AFDX communications protocol past, present and future. AFDX is the recent replacement technology for ARINC 429. The gradual move to Ethernet and distributed computing in commercial and military aerospace projects has hinted for many years at the eventual development of AFDX. However, it was not until ARINC 664 Part 7 was issued on June 27, 2005 that AFDX was formally defined as a standard. ARINC and the AEEC, working with the industry, created a deterministic protocol for real time application on Ethernet media, which is now recognized by most of key aerospace players as ARINC 664 Part 7 or AFDX.
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PDP-8 on an FPGA: A case study in obsolescence management.
Obsolescence affects all systems, today’s bleeding edge technology will soon be a component of a
legacy system. Whether legacy is a positive or pejorative term is of course a topic of current
debate. The positive perspective of legacy systems is that they have real value in that they are
validated and work, possess an implicit specification endorsed by their user community, provide a
basis for incremental enhancement, and have well defined costs. The pejorative perspective
perceives legacy systems as comprising ageing components with high support costs, which are
based on arcane technologies and methodologies, supported by a dwindling band of high priests,
and possessing the capability to undermine the mission at any time. Implicit in these perspectives
are the evolutionary and big bang theories of system evolution. A balanced view is of course
more nuanced: sometimes the system’s match to mission needs provides an unequivocal answer,
perhaps technology refresh is required to address supportability issues, alternatively perhaps
reverse engineering and skilled documentation would enable effective maintenance, and of course
proven software is worth much more than an executable requirements specification.
The presentation will review contemporary perspectives on obsolescence management and legacy
systems. Using the re-implementation of a classic 1960’s minicomputer on an FPGA as an
exemplar, the implementation of powerful HCI capabilities on a host PC and the negligible
infrastructure required to realise them will be described and demonstrated. Specifically, a diskless
Digital PDP 8/E will be demonstrated as a system on a chip with a PC hosting a superset of the
original blinkenlites and switches console.
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Significant developments in the Defence Electronics markets.
This presentation will explore significant developments in the Defence Electronics markets.
It will first outline the significance of battlefield digitisation and explain the key military operational concepts that underpin this.
Christopher Dabrowski will then move on to discuss the ‘defence industrial ecosystem,’ and how these dynamics are catalysing
the transformation of the defence value-chain. These themes will then be discussed in the context of air mobility/strike and
communications procurements. This session will conclude with an overview of the opportunities that this 'value-chain transformation' creates.
The ensuing Q&A discussion is intended to elaborate the points discussed while providing a better understanding of how to turn change trends
into revenue-generating opportunities.
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TS 62239 Avionics Electronics Component Management Plans
TS 62239 Avionics Electronics Component Management Plans is a new international Standard describing a methodology which recognises the increasing difficulty in procuring high reliability electronic components for the Aerospace industry. It provides criteria for OEMs to assess commercially available components, particularly semiconductors, which are now inevitably required to perform reliably in the onerous conditions specified by the avionics, aerospace, military and similar industries.
TS 62239 has been developed by the IEC Avionics Implementation Working Group (AIWG) which includes representation from all interested parties in the aerospace industry. In fact vital support was provided from Boeing and Airbus who provided a committee Chairman and Secretary respectively.
The Standard covers eight vital areas:
- Component Selection
- Component Application
- Component Qualification
- Component Quality Assurance
- Component Dependability (eg: reliability, obsolescence etc)
- Component / Process Compatibility (eg: Pb-free, MSL, ESD issues)
- Component Data
- Configuration Control
Certification for Avionics OEMs is being offered through IECQ with key industry players already holding certificates; Honeywell, Smiths Aerospace, Goodrich and Northrop Grumman.
With fewer Military and other third party approved components, and the general move to COTS procurement, this Standard provides an important tool for high reliability product assurance.
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